dynamic-CMOS circuit

Lab 2
Size the NFETs in the following dynamic-CMOS circuit.
• Download http://eecs.wsu.edu/~ee434/Labs/lab2.zip and unzip it. There is
lab2.sp. Use the netlist. You can change the widths of the NFETs in the netlist.
• Do not touch anything else except the widths of the NFETs.
• The width of a 1X transistor is 50nm.
• The width of each NFET should be an integer multiple of 50nm. For example,
you can use 100nm (2X), 250nm (5X), etc., but you cannot use 67nm, 271nm, etc.
• Objective: Minimize the total width of the NFETs.
• Constraint: For each path, the fall delay should be less than or equal to 60ps.
• Use HSpice to simulate it.
• What to submit
o Final netlist.
Grading criteria
• If all the paths satisfy the timing constraint:
o Total area (A) <= 10,500nm: 100 points
o 10,500nm < A <= 10,550nm: 95 points
o 10,550nm < A <= 10,600nm: 90 points
o etc.
• If some of the paths do not satisfy the timing constraint:
o A <= 10,500nm: 100 points – 2*∑( − 60) (Sum is for all the
violating paths)
o 10,500nm < A <= 10,550nm: 95 points – 2*∑( − 60)
o etc.